FIG. 1 shows a data transmission system according to the prior art. A transceiver or a transmitter and receiver circuit receives transmit data from a data source and transmits this data to another transceiver as an analog transmit signal via a data transmission line. The data transmission line is, for example, a two-wire telephone line made of copper. The transceiver at the COT (central office terminal) end constitutes here the clock master, i.e. the transmitted transmit signal is emitted in synchronism with a clock signal of the transceiver at the COT end. The transceiver at the subscriber end RT forms what is referred to as the clock slave, i.e. the clock signal which is received at the reception end is used as its transmission clock.
When there is fault-free synchronization of the transceiver RT at the subscriber end, the clock frequency of the transmit signal coincides precisely with the clock frequency of the received signal. For this reason, the clock control circuit of the COT end transceiver only has to set the precise sampling phase in the receiver contained in it. The sampling phase depends here especially on the signal transit time of the transmission line.
In the data transmission system illustrated in FIG. 1, the data is transmitted simultaneously in both directions via the transmission line. It is therefore what is referred to as a full duplex data transmission system. The analog received signal of a transceiver is composed here of two signal components, namely of the transmit signal which is emitted by the transceiver at the opposite end, and of the signal component or the echo signal component which is fed in by the system's own transmitter device. The echo signal component constitutes signal interference here and is compensated in the receiver of the transceiver by means of an echo compensation circuit. The echo compensation circuit within the transceiver calculates the most precise estimated value possible for the echo signal component and subtracts it from the received signal.
FIG. 2 shows a conventional transceiver according to the prior art. The transceiver is composed of a transmit signal path and a received signal path. The transmit data or transmit data symbols are firstly fed to a transmission filter in the transmit signal path and then converted into an analog transmit signal by means of a digital-to-analog converter. The analog transmit signal is output to a hybrid network, after amplification with a driver circuit. The hybrid network is connected to the data transmission line.
The received analog signal is firstly filtered on the received signal path by means of an analog reception filter EF, and subsequently sampled. The sampling is carried out within a sampling circuit which is composed either of an analog-to-digital converter or, as illustrated in FIG. 2, of an analog-to-digital converter, an interpolation filter IF and a downstream interpolator. The analog-to-digital converter samples the analog received signal here with a freewheeling working clock signal. The sampled signal is then fed to the digital interpolation filter IF and interpolated by means of the interpolator. For this purpose, a controlled sampling clock signal is fed to the interpolator.
A subtractor circuit A which subtracts the estimated signal calculated by the echo compensation circuit from the sampled digital received signal by generating an echo-compensated digital received signal is connected downstream of the sampling circuit. The echo compensation circuit calculates the expected echo signal by means of the received transmission data symbols and subtracts said echo signal from the received signal. The echo compensation circuit can generally be set in an adaptive fashion. The echo compensation circuit is set in an adaptive fashion in accordance with the transmission function of the transmission line and the analog component, for example the transformer.
The difference signal which is formed by the subtractor A is fed to an amplitude control circuit AGC (Automatic Gain Control). The digital received signal whose amplitude is controlled is then equalized by means of an equalizer. The downstream decision element determines, from the equalized received signal, an estimated value for the transmit data symbol which is originally emitted by the other transceiver. The acquired transmit data symbol is output to the data sink for further data processing by the transceiver. A subtractor forms differences between the signal values upstream and downstream of the decision element. This fault signal or deviation signal is used as a setting signal for the echo compensation circuit. As described in EP 0 144 067 B1, either the difference signal which is formed by the subtractor A or the difference signal which is formed by the subtractor B can be used for the setting signal of the echo compensation circuit. Switching via between the two setting possibilities is carried out by means of a changevia switch.
In order to control the sampling phase of the received signal, a clock control criterion or a clock adjustment control signal is generated by means of a control circuit. The clock adjustment control signal specifies the phase deviation between the signal phase of the sampling clock signal and a desired setpoint signal phase of an ideal sampling clock signal. The clock control criterion or the clock control signal is a measure of the phase error between the ideal sampling clock in which there is a maximum signal-to-noise ratio, and the actual sampling clock. The clock adjustment control signal is generated from the sampled values upstream and downstream of the decision element (decision-fed-back control) and in addition from at least one of the coefficients of the linear equalizer EQ by means of the control circuit. The clock control criterion or the clock adjustment control signal is composed here of two components, namely of a signal component which is dependent on the sampled values upstream and downstream of the decision element and of a second signal component which is both dependent on one or more coefficients of the linear equalizer and on a suitably predefined phase reference signal value which is applied to the control circuit. When the sampling phase is set in an optimum way, the signal component which is dependent on the coefficient corresponds to the predefined phase reference signal value. The control signal therefore continuously generates a control variable which constitutes a measure of the deviation of the sampling phase from the setpoint phase.
The generated clock adjustment control signal is output to a digital loop filter. The output signal of the loop filter directly controls the sampling phase of the sampling clock signal for the sampling circuit. This is generally implemented using a phase counter. The counter reading of the phase counter defines here the phase difference between the transmission phase and the reception phase. In the steady state, the counter reading of the phase counter is largely constant in accordance with the constant phase difference between the phase of the transmit signal and the phase of the received signal. This constant phase difference depends on the signal transit time of the transmission line.
In the case of a clock phase control step within the transceiver at the COT end, the reception phase or the phase of the digital received signal is changed with respect to the phase of the transmit signal. Since the echo signal which is fed in is received with the phase of the transmit signal, each adjustment of the clock phase is also accompanied by a change in the echo signal which is sampled using the reception clock. The transceiver at the COT end therefore has a high degree of coupling of the clock phase control circuit to the echo compensation circuit EC. After the phase change, the echo compensation circuit is to be set again and the equalizer EQ must be re-synchronized again as far as possible.
The sampling phase control circuit of the transceiver according to the prior art illustrated in FIG. 2 is therefore relatively slow-acting so that the transceiver according to the prior art requires a relatively long synchronization time.